Job description
Description
WE’RE HIRING!
At HTG, you’ll push boundaries with the latest tech and collaborate with a team that loves what they do. Be part of a design services company that is amongst the companies that lead the world in technology and innovation.
Your next chapter starts here.
Your responsibilities include:
Read and understand the architecture and functional requirements specification document(s) and communicate and collaborate with systems engineers and architects.
Thoroughly validate one or more architectural functional blocks using a combination of simulation, formal, and coverage methods.
Develop verification, functional coverage and formal verification test plans.
Create testbench environments and components, agents, scoreboard, and test scenarios using System Verilog UVM and/or C.
Perform coverage-driven verification, monitor regressions, and debug failures with the support of the function’s designer.
Provide regular status updates on verification progress on a regular basis.
Requirements
8 to 12 years of experience in ASIC Verification Engineering
Demonstrated experience in the use of System Verilog for hardware design and verification.
Proven proficiency with UVM (Universal Verification Methodology ) environments and methodologies.
Solid programming experience in C and Python.
Strong analytical and problem-solving skills with the ability to address complex technical challenges effectively.
High Tech Genesis Inc. is an Equal Opportunity Employer committed to building inclusive teams where diverse perspectives drive innovation.
We support an accessible recruitment process and are happy to provide accommodation upon request.
Applicants must be legally authorized to work in Canada, and resumes should be submitted in Microsoft Word format.
